Czochralski (Cz) silicon wafers are the material most commonly used for integrated circuits (ICs) due to their internal gettering (IG) ability associated with oxygen precipitates. Metal contamination is inevitable during the fabrication of ICs. However, if metal contaminants cannot be removed from the active regions of the device, the fabrication yield of ICs will be significantly reduced. To solve this problem, normally a high density of oxygen precipitates and oxygen precipitation induced defects will be formed in the bulk of the silicon wafer (referred to as bulk microdefect (BMD) zone), while an oxygen-precipitate-free region (referred to as denuded zone, DZ) will be created in the near-surface region of the silicon wafer where the device active area resides. The oxygen precipitates and oxygen precipitation induced defects in the bulk of the silicon wafer will act as the gettering sites for the metal contaminants in the device active area. This is commonly referred to as IG. Generally, the heat treatment process that leads to the formation of the DZ and the BMD zone in the Cz silicon wafers is called IG process.
Currently, there are two mainstreams of IG processes for Cz silicon wafers. The first one is the high-low-high temperature (H-L-H) three-step annealing process. First, a Cz silicon wafer is annealed at 1100-1200° C. for several hours so as to let oxygen out-diffuse from the near-surface region of the silicon wafer, thereby reducing the oxygen concentration and in turn preventing the oxygen precipitation in the near-surface region. The purpose of this high temperature annealing is to form a DZ. The Cz silicon wafer is then annealed at 600-800° C. for several hours to enable the nucleation of oxygen precipitates in the bulk of the silicon wafer. During this low temperature annealing, the nucleation of oxygen precipitates in the near-surface region of the silicon wafer becomes very difficult due to the low oxygen concentration in this region. Finally, the Cz silicon wafer is annealed at 1000-1100° C. for a relatively long time (e. g., 16 h) to allow the growth of oxygen precipitate nuclei to form oxygen precipitates and oxygen precipitation induced defects in the bulk of the silicon wafer. No oxygen precipitates will be formed in the near-surface region of the silicon wafer at this step. During this high temperature annealing, secondary defects such as punched-out dislocations are generally induced. It is well-known that the IG process based on H-L-H three-step annealing is very time-consuming and has a high thermal budget.
The second type is the “Magic Denuded Zone™ (MDZ™)” process, which features the use of a rapid thermal processing (RTP) at high temperature developed by an American company, MEMC. In a typical process, a silicon wafer is first subjected to the RTP at 1250° C. for 60 seconds under an argon atmosphere, and then cooled at a certain rate. At this step, a high concentration of vacancies is generated in the bulk of the silicon wafer. Due to the out-diffusion of the vacancies, the vacancy concentration is gradually decreased from the bulk to the surface of the silicon wafer with a relatively low vacancy concentration at the surface. This vacancy concentration profile has a full control over the oxygen precipitation behavior of the wafer. That is, above a critical concentration, the vacancies sharply enhance the nucleation of oxygen precipitates. The silicon wafer is then annealed at 800° C. for 4 hours. At this annealing step, the relatively high vacancy concentration in the bulk of the silicon wafer can facilitate the formation of the oxygen precipitate nuclei, while no oxygen precipitate nuclei will be formed in the near-surface region of the silicon wafer due to the relatively low vacancy concentration in this region. Finally, the silicon wafer is annealed at 1000° C. for 16 h to form oxygen precipitates and oxygen precipitation induced defects in the bulk but not in the near-surface region of the silicon wafer. The advantage of “MDZ™” process is that the width of the DZ and the density of oxygen precipitates can be simply controlled by the cooling rate of the RTP. Moreover, this IG process, unlike the traditional H-L-H process, is nearly independent on the oxygen concentration and thermal history of the silicon wafer.
Comparing to the conventional H-L-H three-step annealing process, the MDZ™ process developed by MEMC can significantly reduce the thermal budget. However, since with ever-smaller feature size of ICs, the thermal budget in the device fabrication needs to be continuously decreased, the IG process for Cz silicon wafers has to be improved to further lower the annealing temperature and shorten the annealing time. Since 200 mm and 300 mm silicon wafers are commonly used in the large scale IC fabrication, a low thermal budget IG process is more important for these silicon wafers.